This invention relates to a comparator for converting a voltage difference appearing between a first and a second input terminal of the comparator during a first state of a clock signal into a voltage difference appearing between a first and a second output terminal of the comparator during a second state of the clock signal, which comparator comprises:
a differential amplifier having a non-inverting and an inverting input and having an inverting and a non-inverting output, which outputs are coupled to a first and a second output terminal, respectively of the comparator,
first and second switching means for coupling the first and the second input terminal to the non-inverting input, and the inverting input respectively, during the first state of the clock signal,
a first and a second capacitor coupled between the inverting output and a first node and between the non-inverting output and a second node respectively, and
third and fourth switching means for coupling the first node to a first reference voltage terminal and the second node to a second reference voltage terminal, respectively, during the first state of the clock signal.
Such a comparator is known from U.S. Pat. No. 4,553,052. Clocked comparators are employed, inter alia, in analog-to-digital converters. In the first state of the clock signal a differential amplifier in the comparator determines whether an input signal is larger or smaller than a specific reference signal. In the second state of the clock signal a decision is made by transferring the output signal of the differential amplifier into a latch. The resolution of an analog-to-digital converter depends inter alia on the accuracy with which the comparators used therein can distinguish between the input signal and the reference. The accuracy is limited, inter alia, by the offset voltage on the input terminals of the differential amplifier. Therefore, it is desirable to reduce the offset voltage of the differential amplifiers in comparators so as to increase the accuracy of analog-to-digital converters.
In the prior art comparator offset reduction is achieved in that in the first state of the clock signal the voltage difference between the input terminals of the comparator, which is amplified by the differential amplifier, together with the equally amplified offset voltage is stored in capacitors arranged between a reference voltage and the outputs of the differential amplifier. Subsequently, in the second state of the clock signal, the inputs of the differential amplifier are interconnected so that this amplifier now only amplifies its own offset, the capacitors being arranged between the outputs of the differential amplifier and the two output terminals. By adding the charges on the capacitors a voltage difference will be available across the output terminals which is independent of the offset voltage of the differential amplifier. This voltage difference controls a latch which decides which of the two output terminals carries the higher voltage. A disadvantage of this known comparator is that the latch itself also exhibits an input offset so that, although the differential voltage is offset free the decision is subject to inaccuracy. Moreover, such a latch requires an additional number of circuit components.